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6.       Active HDL.

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(stored program electronic computer) , (); ( ) . , - . -.

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1. JMP # ;

2. MOV A, #d ;

3. MOV Rn, #d ;

4. RL ;

:

- 51.

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- #d ;

- n 0 , 1, 2, 3;

- bit 7, 6, 5, 4, 3, 2, 1, 0.

.1. ( , ). 4- () R0-R3, , , .

, , , (AccIn, ALURL, RegIn, PCIn, PCInc, MBROut, IRIn, MemRd, Reset).

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2.        

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, :

7 6 5 4 3 2 1 0

:

0 0 Jmp #
0 1 Mov A,#
1 0 Mov Rn,#
1 1 Rl A

JMP #d:


MOV A, #d:


MOV Rn, #d:

RL A:


4

:

(JMP #d)

1    MemRd, PCInc ( , )

2    MBROut, IRIn ( MBR, )

3    MemRd, PCInc ( , )

4    MBROut, PCIn ( MBR)

5    Reset ()

(MOV A, #d)

1    MemRd, PCInc ( , )

2    MBROut, IRIn ( MBR, )

3    MemRd, PCInc ( , )

4    MBROut, AccIn, Reset ( MBR, , )

(MOV Rn, #d)

1    MemRd, PCInc ( , )

2    MBROut, IRIn ( MBR, )

3    MemRd, PCInc ( , )

4    MBROut, RegIn, Reset ( MBR, , )

(RL A)

1    MemRd, PCInc ( , )

2    MBROut, IRIn ( MBR, )

3    MemRd, PCInc ( , )

4    MBROut ( MBR)

5    ALUOP, AccIn, Reset ( , , )

5

. 2.


. 2.

:

MemRd<='1' when c="00000001" or c="00000100" else '0' after 5ns;

PCInc<='1' when c="00000001" or c="00000100" else '0' after 5ns;

MBROut<='1' when c="00000010" or c="00001000" else '0' after 5ns;

IrIn<='1' when c="00000010" else '0' after 5ns;

PCIn<='1' when c="00001000" and i="0001" else '0' after 5ns;

AccIn<='1' when (c="00001000" and i="0010") or (c="00010000" and i="1000") else '0' after 5ns;

RegIn<='1' when c="00001000" and i="0100" else '0' after 5ns;

ALURL<='1' when c="00010000" and i="1000" else '0' after 5ns;

Reset<='1' when (c="00010000" and i="0001") or (c="00010000" and i="1000")

or (c="00001000" and i="0010")or (c="00001000" and i="0100") else '0' after 5ns;

6 ACTIVE HDL

, , :

library ieee;

use ieee.std_logic_1164.all;

entity MAR is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

RST: in std_logic;

Clk: in std_logic);

end MAR;

architecture MAR of MAR is

signal master, slave: std_logic_vector(7 downto 0);

begin

Q<=slave;

process(D,RST,Clk)

begin

if Clk='0' then

if RST='1'then master<=(others => '0') after 2ns;

else master<=D after 2ns;

end if;

end if;

end process;

process(master,Clk)

begin

if Clk='1'then slave<=master after 2ns;

end if;

end process;

end architecture MAR;

----------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

entity REGI is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EI: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end REGI;

architecture REGI of REGI is

signal master, slave: std_logic_vector(7 downto 0);

begin

Q<=slave;

process(D,RST,Clk,EI)

begin

if Clk='0'then

if RST='1' then master<=(others => '0') after 2ns;

elsif EI='1' then master<=D after 2ns;

end if;

end if;

end process;

process(master,Clk)

begin

if Clk='1'then slave<=master after 2ns;

end if;

end process;

end architecture REGI;

----------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

entity MBR is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EO: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end MBR;

architecture MBR of MBR is

signal master, slave: std_logic_vector(7 downto 0);

begin

process(D,RST,Clk)

begin

if Clk='0'then

if RST='1' then master<=(others => '0') after 2ns;

else master<=D after 2ns;

end if;

end if;

end process;

process(master,Clk)

begin

if Clk='1'then slave<=master after 2ns;

end if;

end process;

process(slave,EO)

begin

if EO='1'then Q<=slave;

else Q<=(others => 'Z');

end if;

end process;

end architecture MBR;

----------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity Counter is

port(Q: out std_logic_vector(2 downto 0);

RST: in std_logic;

Clk: in std_logic);

end Counter;

architecture Counter of Counter is

signal master, slave, slave_inc: std_logic_vector(2 downto 0);

begin

Q<=slave;

slave_inc<=slave+1 after 2ns;

process(slave_inc,RST,Clk)

begin

if Clk='0'then

if RST='1'then master<=(others => '0') after 2ns;

else master<=slave_inc after 2ns;

end if;

end if;

end process;

process(master,Clk)

begin

if Clk='1' then slave<=master after 2ns;

end if;

end process;

end Counter;

----------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity PC is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EI: in std_logic;

Inc: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end PC;

architecture PC of PC is

signal master, slave, slave_inc: std_logic_vector(7 downto 0);

begin

Q<=slave;

slave_inc<=slave+1 after 2ns;

process(D,RST,Clk,EI,Inc,slave_inc)

begin

if Clk='0' then

if RST='1' then master<=(others => '0') after 2ns;

elsif EI='1' then master<=D after 2ns;

elsif Inc='1' then master<=slave_inc after 2ns;

end if;

end if;

end process;

process(master,Clk)

begin

if Clk='1'then slave<=master after 2ns;

end if;

end process;

end PC;

----------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity Decoder is

generic(n: integer:=2);

port(D: in std_logic_vector(n-1 downto 0);

Q: out std_logic_vector((2**n)-1 downto 0));

end Decoder;

architecture Decoder of Decoder is

begin

process(D)

variable i:integer;

variable s:bit_vector((2**n)-1 downto 0);

begin

s:=(0 => '1', others => '0');

i:=conv_integer(D);

s:=s rol i;

for ind in 2**n-1 downto 0 loop

if s(ind)='0' then Q(ind)<='0' after 2ns;

else Q(ind)<='1' after 2ns;

end if;

end loop;

end process;

end architecture;

----------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity MUX is

port(D: in std_logic_vector(1 downto 0);

P: in std_logic;

Q: out std_logic_vector(3 downto 0));

end MUX;

architecture MUX of MUX is

begin

process(D,P)

variable i:integer;

variable s:bit_vector(3 downto 0);

begin

s:=(0 => '1', others => '0');

i:=conv_integer(D);

s:=s rol i;

for ind in 3 downto 0 loop

if s(ind)='0' then Q(ind)<='0' after 2ns;

else Q(ind)<=P after 2ns;

end if;

end loop;

end process;

end architecture MUX;

----------------------------------------------------------------------------------

:

library ieee;

use ieee.std_logic_1164.all;

entity BlockRG is

port(D: in std_logic_vector(7 downto 0);

Addr: in std_logic_vector(1 downto 0);

EI: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end BlockRG;

architecture BlockRG of BlockRG is

signal Enable: std_logic_vector(3 downto 0);

component REGI is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EI: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end component REGI;

component MUX is

port(D: in std_logic_vector(1 downto 0);

P: in std_logic;

Q: out std_logic_vector(3 downto 0));

end component MUX;

begin

Registers: for i in 3 downto 0 generate

Reg: REGI port map(D=>D,Q=>open,EI=>Enable(i),RST=>RST,Clk=>Clk);

end generate;

Switch: MUX port map(D=>Addr,P=>EI,Q=>Enable);

end BlockRG;

:

library ieee;

use ieee.std_logic_1164.all;


entity ALU is

port(In1: in std_logic_vector(7 downto 0);

OP: in std_logic;

Res: out std_logic_vector(7 downto 0);

RST: in std_logic;

Clk: in std_logic);

end ALU;

architecture ALU of ALU is

signal RL :std_logic_vector(7 downto 0);

component MBR is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EO: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end component;

begin

DD0:for i in 7 downto 1 generate

RL(i)<=In1(i-1);

end generate;

RL(0) <= In1(7) after 10ns;

BUFF: MBR port map(D=>RL,Q=>Res,EO=>OP,RST=>RST,Clk=>Clk);

end architecture;

:


14,5 ns.

Memory:

library IEEE;

use IEEE.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity Memory is

generic(file_name: string:= "MEM.DAT");

port (addr: in std_logic_vector(7 downto 0);

data: out std_logic_vector(7 downto 0);

rd: in std_logic;

ld: in std_logic);

end Memory;

architecture Memory of Memory is

type t_rom_data is array (15 downto 0) of std_logic_vector(7 downto 0);

type rom_file_type is file of character;

file rom_file: rom_file_type;

signal rom_data: t_rom_data;

begin

process(addr,rd)

variable i: natural;

begin

if rd = '1' then

i := conv_integer(addr);

data <= rom_data(i) after 5ns;

else

data <= (others => 'Z');

end if;

end process;

process(ld)

variable c: character;

begin

if ld='1' then file_open(rom_file,file_name,read_mode);

for i in 0 to 15 loop

for b in 7 downto 0 loop

c:='U';

if not(endfile(rom_file)) then read(rom_file,c);

while not(endfile(rom_file)) and c/='0' and c/='1' and c/='Z' and c/='W'

and c/='L' and c/='H' and c/='-' and c/='X' and c/='U' loop

read(rom_file,c);

end loop;

end if;

if c='0' then rom_data(i)(b) <= '0';

elsif c='1' then rom_data(i)(b) <='1';

elsif c='Z' then rom_data(i)(b) <='Z';

elsif c='W' then rom_data(i)(b) <='W';

elsif c='L' then rom_data(i)(b) <='L';

elsif c='H' then rom_data(i)(b) <='H';

elsif c='-' then rom_data(i)(b) <='-';

elsif c='X' then rom_data(i)(b) <='X';

else rom_data(i)(b) <='U';

end if;

end loop;

end loop;

file_close(rom_file);

end if;

end process;

end Memory;

:

:


library ieee;

use ieee.std_logic_1164.all;

entity CU is

port(Instr: in std_logic_vector(1 downto 0);

AccIn: out std_logic;

ALURL: out std_logic;

RegIn: out std_logic;

PCIn: out std_logic;

PCInc: out std_logic;

MBROut: out std_logic;

IRIn: out std_logic;

MEMRd: out std_logic;

Reset: inout std_logic;

RST: in std_logic;

Clk: in std_logic);

end CU;

architecture CU of CU is

signal R: std_logic;

signal InstrDecoded,i: std_logic_vector(3 downto 0);

signal CounterPacked: std_logic_vector(2 downto 0);

signal CounterDecoded,c: std_logic_vector(7 downto 0);

component Counter is

port(Q: out std_logic_vector(2 downto 0);

RST: in std_logic;

Clk: in std_logic);

end component;

component Decoder is

generic(n: integer:=2);

port(D: in std_logic_vector(n-1 downto 0);

Q: out std_logic_vector((2**n)-1 downto 0));

end component;

begin

DD0: Counter port map(Q=>CounterPacked,RST=>R,Clk=>Clk);

InstrDecoder: Decoder generic map(2)port map(D=>Instr,Q=>InstrDecoded);

CounterDecoder: Decoder generic map(3)port map(D=>CounterPacked,Q=>CounterDecoded);

c<=CounterDecoded;

i<=InstrDecoded;

MemRd<='1' when c="00000001" or c="00000100" else '0' after 5ns;

PCInc<='1' when c="00000001" or c="00000100" else '0' after 5ns;

MBROut<='1' when c="00000010" or c="00001000" else '0' after 5ns;

IrIn<='1' when c="00000010" else '0' after 5ns;

PCIn<='1' when c="00001000" and i="0001" else '0' after 5ns;

AccIn<='1' when (c="00001000" and i="0010") or (c="00010000" and i="1000") else '0' after 5ns;

RegIn<='1' when c="00001000" and i="0100" else '0' after 5ns;

ALURL<='1' when c="00010000" and i="1000" else '0' after 5ns;

Reset<='1' when (c="00010000" and i="0001") or (c="00010000" and i="1000")

or (c="00001000" and i="0010")or (c="00001000" and i="0100") else '0' after 5ns;

R<=RST or Reset;

end architecture;


7

:

library ieee;

use ieee.std_logic_1164.all;

entity CPU is

generic(file_name: string:=".\src\MEM.DAT");

port(RST: in std_logic;

Clk: in std_logic);

end entity;

architecture CPU of CPU is

-----------------------------------------------------------

component MAR is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

RST: in std_logic;

Clk: in std_logic);

end component;

-----------------------------------------------------------

component REGI is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EI: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end component;

------------------------------------------------------------

component MBR is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EO: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end component;

-------------------------------------------------------------

component PC is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EI: in std_logic;

Inc: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end component;

--------------------------------------------------------------

component ALU is

port(In1: in std_logic_vector(7 downto 0);

OP: in std_logic;

Res: out std_logic_vector(7 downto 0);

RST: in std_logic;

Clk: in std_logic);

end component;

---------------------------------------------------------------

component BlockRG is

port(D: in std_logic_vector(7 downto 0);

Addr: in std_logic_vector(1 downto 0);

EI: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end component;

----------------------------------------------------------------

component Memory is

generic(file_name: string:= "MEM.DAT");

port (addr: in std_logic_vector(7 downto 0);

data: out std_logic_vector(7 downto 0);

rd: in std_logic;

ld: in std_logic);

end component;

-----------------------------------------------------------------

component CU is

port(Instr: in std_logic_vector(1 downto 0);

AccIn: out std_logic;

ALURL: out std_logic;

RegIn: out std_logic;

PCIn: out std_logic;

PCInc: out std_logic;

MBROut: out std_logic;

IRIn: out std_logic;

MEMRd: out std_logic;

Reset: inout std_logic;

RST: in std_logic;

Clk: in std_logic);

end component;

signal AccIn,ALURL,RegIn,PCIn,PCInc,MBROut,IRIn,MEMRd,Reset:std_logic;

signal Inst_Addr:std_logic_vector(7 downto 0);

signal mem_mbr,BUS1,pc_mar,mar_mem,acc_alu:std_logic_vector(7 downto 0);

begin

DD0: CU port map(Instr=> Inst_Addr(7 downto 6),AccIn=> AccIn,ALURL=> ALURL,

RegIn=> RegIn,PCIn=> PCIn,PCInc=> PCInc,MBROut=> MBROut,IRIn=> IRIn,

MEMRd=> MEMRd,Reset =>Reset,RST => RST, Clk => Clk);

DD1: ALU port map(In1=> acc_alu,OP=> ALURL,Res=> BUS1,RST=> RST,Clk => Clk);

DD2: Memory generic map(file_name)port map(addr => mar_mem,data => mem_mbr,rd=> MEMRd,ld=> RST);

DD3: BlockRG port map(D => BUS1,Addr=> Inst_Addr(5 downto 4),EI => RegIn,RST=> RST,Clk=> Clk);

IR: REGI port map(D => BUS1,Q=> Inst_Addr,EI=> IRIn,RST => RST, Clk => Clk);

DD4: MBR port map(D=> mem_mbr,Q=> BUS1,EO=> MBROut,RST => RST, Clk => Clk);

DD5: MAR port map(D => pc_mar,Q => mar_mem,RST => RST, Clk => Clk);

DD6: PC port map(D=> BUS1,Q => pc_mar,EI=> PCIn,Inc => PCInc,RST=> RST,Clk=> Clk);

ACC: REGI port map(D=> BUS1,Q=> acc_alu,EI=> AccIn,RST=> RST,Clk=> Clk);

end CPU;

Mem.dat, , VHDL. .

01.00.0000 11111111 ;mov a,#

10.00.0000 00000001 ;mov ro,#

10.01.0000 00000010 ;mov rl,#

10.10.0000 00000100 ;mov r2,#

10.11.0000 00001000 ;mov r3,#

01.00.0000 00000001 ;mov a,#

11.00.0000 00000000 ;rl a

00.00.0000 00001100 ;jmp #

, , std_logic. , 2 , 2 - ), . .

, , , JMP.

. 3, data . . 4. .


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, 100 ns, 125 ns. 1050 ns.





2010